The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs or MOS transistors). A MOS transistor includes a gate electrode as a control electrode overlying a semiconductor substrate and spaced-apart source and drain regions in the substrate between which a current can flow. A gate insulator is disposed between the gate electrode and the semiconductor substrate to electrically isolate the gate electrode from the substrate. A control voltage applied to the gate electrode controls the flow of current through a channel in the substrate underlying the gate electrode between the source and drain regions.
ICs can include both resistors and transistors. In a field effect transistor, metal silicide regions are typically formed in the source/drain regions of a transistor to reduce the resistance when a conductive contact is formed to establish electrical connection to the source/drain regions. A resist protection oxide can be used to block silicide formation of an electrostatic discharge transistor. In a resistor, the electrical resistance of the resistor can be controlled, or maintained within a desirable range by forming a metal silicide region.
However, the metal silicide layer in both resistors and transistors can impart large variations in electrical performance as compared to other devices. These variations can be caused by physical deviations in the formation of the metal silicide layer or chemical properties of the ICs. There can be several sources of this variation, including the critical dimension and/or overlay of the implantation layer and the resist protection oxide layer, the resist protection oxide etch, and the lower doping concentration of the resistor body or electrostatic discharge transistor. Although there is no silicide formation at the resist protection oxide covered region, doping limits the resistivity of the high resistive path, resulting in an area penalty. Hence, reducing variation in metal silicide formation can reduce variation in IC performance.
Accordingly, it is desirable to provide a method for fabricating integrated circuits or components that have reduced variation in metal silicide formation. In addition, it is desirable to form the metal silicide outside of at least one gate. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.